Technical Field
The invention relates to a device and a method for storing data in a plurality of multi-level cell memory chips, each of the multi-level cell memory chips having a plurality of memory cells, each memory cell having a plurality of programmable levels.
Related Art
A multi-level cell (MLC) is a memory element capable of storing more than a single bit of information. This is achieved by using multiple levels per cell to allow more bits to be stored in each cell. A MLC memory chip may comprise a plurality of memory cells. A plurality of MLC memory chips may form a MLC memory array.
In order to retrieve information reliably from an MLC memory cell, it may be desirable to have an estimation of the channel statistics being used for the detection and decoding algorithms. This may be, in particular, useful if the channel statistics are not stationary in time and cannot be determined by characterization, for example, the drift effect in Phase Change Memory (PCM). If data is read from and written to a memory cell in small chunks of data (e.g., 32 cells), then it is possible that one of the MLC levels (or states) is only written a small number of times or even not at all. This data asymmetry can make it very difficult to estimate channel statistics. It may thus be desired that it is programmed, e.g., written, to all MLC levels as many times as possible.
One solution might be to use a balanced code to ensure that each MLC level is written the same number of times. However, the coding overhead required to balance the data sequence is very high for the small block lengths required by memory applications. Another solution might be to perform enumerative encoding and decoding to ensure that each level is written a least k times. This would be very efficient in terms of coding rate, but the encoders/decoders are not suitable for low-latency memory applications and may suffer from error propagation, for instance, as errors in the read-back data can lead to a decoding failure.
U.S. Pat. No. 8,578,243 B2 discloses a method for data storage including defining a set of scrambling sequences. Each data word is scrambled using a respective scrambling sequence selected from the set and the level of randomness of the scrambled data word is determined. If the level of randomness is determined to be less than some pre-determined level of randomness, then the scrambled data word is stored in a memory device. The level of randomness is defined to be the balancing degree of the scrambled data word. Such a method can ensure that the scrambled data word is close to balanced, however if the scrambled data word is split into sub-words and stored across multiple chips, it is possible for the sub-words to be highly asymmetric. In order to solve this problem, one might perform the same method of scrambling, but on the sub-words rather than on the sequence itself. However, since there is some overhead involved in the scrambling method, this approach might be inefficient.
Accordingly, it is an aspect of the present invention to provide a device and a method for storing data across multiple memory chips and improving the symmetry of data across the memory levels.